ASIC / FPGA Design Verification Engineer - 1809 (New York)

  • Address:New York, NY 10004 (map)
  • Date Posted:08/30/16
  • Job Type:Full-time
  • Description:
  • Job Title: ASIC / FPGA Design Verification EngineerLocation: New York, NYType: PermDescription:Seeking Design Verification Engineer with 5+ years experience of verification of high-speed ASIC designs. Opportunity is with excellent company providing above market compensation.Requirements:- 5+ years Design Verification Experience- Experience on large, complex high-performance chips- System Verilog CRV- Experience one of the following tools: VCS, Questa, or Incisive, Verilog- CDC (Clock domain crossing)- linting, DRC, Spyglass, DFT (Design for Test), VIP- Experience with scripting languages- Masters or PhD in EE or Computer Engineering or Related Field- Power Management background desired- OVM, VMM, or UVM- Experience with scripting languages: Perl, Python, and/or Tcl.Relevant methodologies include model checking, equivalence checking, and property checking , and relevant tools include Mentor Questa Formal, Cadence Incisive Formal Verifier (IFV), JasperGold, Synopsys Magellan, and VC Formal.A plus: C++To apply for this position please submit an MS Word doc of your resume and put in the subject "Job ID # 1809".Or go to our website at to submit your resume with the Job ID number in the subject.  
Ad ID: 45808966
  • Posted by: Ad Partner | View all ads
  • Profile: Active since 08/2016
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